Exploring Cortex-M Microarchitectural Side Channel Information Leakage

The growing Internet of Things (IoT) market demands side-channel attack resistant, efficient, cryptographic implementations. Such implementations, however, are microarchitecture-specific, and cannot be implemented without an in-depth structural knowledge the CPU memory information leakage patterns; a description such leakages is presently not disclosed by any processor design company. In this work we propose first Instruction Set Architecture (ISA) level framework for microarchitectural characterization. Our allows to extract profile from superscalar in-order processor; infer detailed pipeline characteristics through observation instruction timings, provide identification datapath registers via measuring setup. extracted model can serve as foundation building solid countermeasures against attacks on software We validate models ARM Cortex-M4 Cortex-M7 CPUs, latter being most powerful microcontrollers offer. Finally, further demonstration our model’s accuracy, mount successful unprotected AES implementations each examined platforms.